1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a nonvolatile ferroelectric memory device and a method for operating the same.
2. Discussion of the Related Art
In general, a nonvolatile ferroelectric memory such as a ferroelectric random access memory (FRAM), for example, has a data processing speed equivalent to that of a dynamic random access memory (DRAM), and the nonvolatile ferroelectric memory retains data during a power OFF state. Accordingly, nonvolatile ferroelectric memories are commonly considered to be one of a next generation of memory devices.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having high residual polarization characteristics. The residual polarization characteristics permit retention of data when an applied electric field is removed.
FIG. 1 illustrates a hysteresis loop of a general ferroelectric material according to the related art. In FIG. 1, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A cell array of a related art nonvolatile ferroelectric memory device and a method for operating the same will now be described with reference to the accompanying drawings. FIG. 2A is a schematic view showing a unit cell of a split wordline SWL according to the related art, FIG. 2B is a circuit diagram illustrating a nonvolatile ferroelectric memory device according to the related art, and FIG. 3 is a timing chart illustrating operation of the nonvolatile ferroelectric memory device according to FIG. 2B.
In FIG. 2A, a unit cell of the nonvolatile ferroelectric memory device has a 1T/1C structure. The unit cell includes first and second split wordlines SWL1 and SWL2 formed with a prescribed interval in a row direction, and first and second bitlines B/L1 and B/L2 formed across and preferably substantially perpendicular to the first and second split wordlines SWL1 and SWL2. A first transistor T1 has a gate coupled with the first split wordline SWL1 and a drain coupled with the first bitline B/L1. A first ferroelectric capacitor FC1 is coupled between a source of the first transistor T1 and the second split wordline SWL2. A second transistor T2 has a gate coupled with the second split wordline SWL2 and drain coupled with the second bitline B2, and a second ferroelectric capacitor FC2 is coupled between a source of the second transistor T2 and the first split wordline SWL1. A plurality of the unit cells constitute a cell array. In view of a data storage unit, a pair of split wordlines and a bitline, a transistor T1, and a ferroelectric capacitor FC1 constitute a unit cell. In view of a data structure, a pair of split wordlines, two bitlines, two transistors, and two ferroelectric capacitors constitute a unit cell.
In FIG. 2B, a plurality of split wordline pairs including first and second split wordlines SWL1 and SWL2 in pairs are preferably formed in row direction. A plurality of bitlines B/L1 and B/L2 are formed across the split wordline pairs. Sensing amplifiers SA are formed between the respective bitlines to sense data transmitted through the bitlines and transfer the sensed data to a data line DL or a data bar line/DL.
At this time, a sensing amplifier enable portion and a selection switching portion CS are provided (not shown). The sensing amplifier enable portion outputs a sensing amplifier enable signal SEN to enable the sensing amplifiers SA, and the selection switching portion CS selectively switches bitlines and data lines.
In FIG. 3, a period t0 denotes a period before the first split wordline SWL1 and the second split wordline SWL2 are activated to “high(H)”. During the period t0, all of the bitlines are preferably precharged to a threshold voltage level of an NMOS transistor.
A period t1 denotes a period in which the first and second split wordlines SWL1 and SWL2 are enabled to become “H”. During the period t1, data of the ferroelectric capacitor in the main cell are transmitted to the main bitline such that the bitline level is varied.
When the ferroelectric capacitor has a logic value “high”, since electric fields having opposite polarities are applied to the bitline and the split wordline, the polarity of the ferroelectric is destroyed so that a large amount of current flows. Thus, a high voltage is induced in the bitline.
By contrast, when the ferroelectric capacitor has a logic value “low”, since electric fields having the same polarities are applied to the bitline and the split wordline, polarity of the ferroelectric is not destroyed so that a small amount of current flows. Thus, a low voltage is induced in the bitline.
During a period t2, if the cell data is loaded in the bitline sufficiently, the sensing amplifier enable signal SEN is transited to high so as to activate the sensing amplifier. As a result, the bitline level is amplified.
Since the logic data “H” of the destroyed cell cannot be restored at the state that the first and second split wordlines SWL1 and SWL2 are high, the data can be restored during a period t3.
Subsequently, during the period t3, the column selection signal CS is activated at “high” level and the bitline of the cell is connected with the data bus line.
During the read mode, the bitline data is transmitted to the data bus. During the write mode, the data bus is transmitted to the bitline.
During the period t3, the first split wordline SWL1 is transited to low, the second split wordline SWL2 is maintained at high level, and the second transistor T2 is turned ON.
At this time, if the corresponding bitline is high, high data is transmitted to one electrode of the second ferroelectric capacitor FC2 so that logic value “1” is restored between the low level of the first split wordline SWL1 and the high level of the bitline.
During a period t4, data of the first bitline BL1 or the second bitline BL2 has a logic value of “0”. The logic value of “0” is written in each ferroelectric capacitor by maintaining the first split wordline at high level.
Meanwhile, when the first bitline BL1 and the second bitline BL2 are high, no changes occur in data of the cell.
During a period t5, the first split wordline SWL1 is maintained at high level and the second split wordline SWL2 is transited to low, and the first transistor T1 is turned ON.
At this time, if the corresponding bitline BL1 is high, high data is transmitted to one electrode of the first ferroelectric capacitor FC1 so that the logic value “1” is restored between the low level of the second split wordline SWL2 and the high level of the first bitline BL1.
A period t6 denotes a precharge period for preparing the next cycle operation.
The aforementioned related art ferroelectric memory device and the method for operating the same have several problems.
Since the wordline driver and the plate line driver are separately operated, the wordline driver has a small delay due to its small size, but the plate line driver causes serious driver RC delay due to its great size.